DRAFT

PhD Thesis Defense

Friday, December 2, 2022
12:00pm to 1:00pm
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Chen 100
Holistic Design in High-Speed Silicon Photonics and Low-Power Electronics Platforms
Arian Hashemi, Graduate Student, Electrical Engineering, California Institute of Technology,

High-speed interconnects are of vital importance to the operation of high-performance computing and communication systems, determining the ultimate bandwidth or data rates at which the information can be exchanged. Optical interconnects and the employment of high order modulation formats are considered as the solutions to fulfilling the envisioned speed and power efficiency of future interconnects. One area of growing importance in optical interconnects is the design and optimization of energy-efficient transmitters with superior power efficiency. Enhancing the electro-optical bandwidth density while keeping the power efficiency optimized, requires improvement in the optical power penalty of photonic integrated circuits. Moreover, co-optimization of electronics and photonics enables a path towards sub-pJ/b transmission efficiency. In this dissertation, architectural and circuit-level energy-efficient techniques serving these goals are presented. First, an integrated 100Gb/s DAC-less PAM-4 transmitter and a 200 Gb/s QAM-16 transmitter in a multi-micron silicon photonics platform using binary-driven SiGe EAMs in an unbalanced MZI are presented. Second, a 100Gb/s PAM4 optical transmitter system implemented in a 3D-integrated Silicon Photonics-CMOS platform is discussed. The photonics chip includes a push-pull segmented Mach-Zehnder Modulator (MZM) structure using highly capacitive, yet optically efficient metal-oxide-silicon capacitor (MOSCAP) phase modulators. Finally, to extend the low-power electronics design to the field of bio-sensing, an efficient biofuel-cell-based energy harvester system, fabricated in 65nm CMOS is presented. The proposed harvester uses no external electrical components and is compatible with biofuel-cell voltage and power ranges. Peak power efficiency of 86% is achieved at 0.39V of input voltage and 1.34μW of output power with 220nW of average power consumption of the chip. The end-to-end power efficiency is kept above 70% for a wide range of loading powers from 1μW to 12μW.

PhD Advisor: Prof. Azita Emami

For more information, please contact Tanya Owen by email at [email protected].